Pressure-Driven Hardware Managed Thread Concurrency for
Irregular Applications
Author/Presenter
Event Type
Workshop
Applications
Architectures
Graph Algorithms
SIGHPC Workshop
TimeMonday, November 13th3:55pm -
4:20pm
Location507
DescriptionGiven the increasing importance of efficient data
intensive computing, we find that modern processor
designs are not well suited to the irregular memory
access patterns found in these algorithms. This research
focuses on mapping the compiler's instruction cost
scheduling logic to hardware managed concurrency
controls in order to minimize pipeline stalls. In this
manner, the hardware modules managing the low-latency
thread concurrency can be directly understood by modern
compilers.
We introduce a thread context switching method that is managed directly via a set of hardware-based mechanisms that are coupled to the compiler instruction scheduler. As individual instructions from a thread execute, their respective cost is accumulated into a control register. Once the register reaches a pre-determined saturation point, the thread is forced to context switch. We evaluate the performance benefits of our approach using a series of 24 benchmarks that exhibit performance acceleration of up to 14.6X.
We introduce a thread context switching method that is managed directly via a set of hardware-based mechanisms that are coupled to the compiler instruction scheduler. As individual instructions from a thread execute, their respective cost is accumulated into a control register. Once the register reaches a pre-determined saturation point, the thread is forced to context switch. We evaluate the performance benefits of our approach using a series of 24 benchmarks that exhibit performance acceleration of up to 14.6X.
Author/Presenter
